Most of the available path-delay fault simulators for scannenvironments rely on the use of augmented scan flip-flops andnexclusively consider circuits composed of only discrete gates. Thisnpaper describes an efficient path-delay fault simulator which operatesnin standard scan environments. The new simulator based on a parallelnpattern fault simulation algorithm can handle the switching devices bynusing new logic values. To achieve high-speed performance, two differentnsets of logic values are used for the element evaluation according tonthe device level. The results show the efficiency of the simulator
展开▼
