High performance double edge-triggered flip-flop using a mergedfeedback technique

摘要

Double edge-triggered flip-flops (DETFFs) use both edges of thenclock to latch data and hence can lead to significant power saving overnsingle edge-triggered flip-flops for a fixed data rate. However,nexisting DETFF implementations suffer from the problems of chargensharing, charge coupling, incomplete voltage swing, poor voltage scalingnproperties and excessive power dissipation. A new DETFF is proposed,nwhich does not suffer from any of these problems and can operate at anclock speed which is 1.33 times that of the best double edge-triggerednflip-flop available today. With reduced supply voltages, this flip-flopnresults in lower power dissipation and maintains a comparablenperformance to, if not better than, existing DETFFs