A design approach for low-voltage SC filters to be implemented in standard CMOS processes is presented. It is based on simple building blocks which are a clock booster and an SC integrator which uses a single-input amplifier instead of the traditional differential-input amplifier. To validate the proposed approach, a fourth-order elliptic SC low-pass filter was designed using a 1.2 /spl mu/m CMOS process and 1.5 V power supply. The measured frequency response accurately agrees with the simulated one in which an infinite-gain amplifier was considered. When the power supply is set to 1.5 V, the filter has a power consumption of 400 /spl mu/W and occupies a silicon area of 0.8 mm/sup 2/.
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机译：提出了一种在标准CMOS工艺中实现的低压SC滤波器的设计方法。它基于简单的构建模块，这些构建模块是时钟增强器和SC积分器，该积分器使用单输入放大器代替传统的差分输入放大器。为了验证所提出的方法，设计了一个四阶椭圆SC低通滤波器，它使用1.2 / spl mu / m CMOS工艺和1.5 V电源供电。测得的频率响应与考虑无限增益放大器的模拟频率响应精确一致。当电源设置为1.5 V时，滤波器的功耗为400 / spl mu / W，硅面积为0.8 mm / sup 2 /。
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