Design methodology for the IBM POWER7 microprocessor

摘要

The IBM POWER7® microprocessor, which is the next-generation IBM POWER® processor, leverages IBM''s 45-nm silicon-on-insulator (SOI) process with embedded dynamic random access memory to achieve industry-leading performance. To deliver this complex 567-$hbox{mm}^{2}$ die, the IBM design team made significant innovations in chip design methodology. This paper describes the most critical methodology innovations specific to POWER7 design, which were in modularity, timing closure, and design efficiency.