Handling 16 instructions per cycle in a superscalar processor

摘要

We present a new partitioning of the processor data path based on a three level separation. First, as in a traditional processor, we separate integer computations from floating point ones. We include in both types data operators, registers, memory and address computation resources. Hence, integer computations are fully disjoint from floating point computations which reduces intra--chip communications. Second, data computation resources are also disjoined from address computation ones. This helps distributing the resource requirements on the data path and on the address path. Third, we separate each register file into two parts. The two sources of every instruction are taken from both parts. The last two separations help keeping the number of necessary resources to handle l6 instructions per cycle (IPC) the same as what is needed today to handle 4 instructions per cycle. Our architectural proposal should allow the implementation of a superscalar degree 16 processor on tomorrows finer design processes.