Hardware Design of Image Channel Denoiser for FPGA Embedded Systems

摘要

Zaproponowano metodę usuwania szumów w systemie FPGA bazującą na algorytmie LMS i 1D-SOI filtrze adapatacyjnym. Przedstawiono możliwości zastosowania metody a gotowym układzie zintegrowanym.%In this article an FPGA-based image channel denoiser using a 1D-standard-LMS algorithm is proposed. The designed core is written in VHDL93 language as basis of 1D-FIR adaptive filter. The proposed core is FPGA-brand-independent, hence can be ported on any brand to create a system-on-chip (SoC). Although using a pure-hardware implementation results in better performance, it is more complex than other structures such as digital signal processors and Hardware/Software co-designs. The results show improvements in area-resource utilization and convergence speed in the designed pure-hardware channel denoiser core.