The Improvement of a Fail-safe Counter for Low-speed Detection

摘要

This paper presents a low-speed detection method by proposing a fail-safe counter. The features of this proposed method were the adoption of digital counter circuits for the detection of low-speed, the diagnosis of the digital counter circuit, and its result output as dynamic signals to a low-pass filter and a charge pump circuit. Moreover, an additional diagnosis of a fail-safe window comparator which evaluated the DC signal level from the charge pump circuit. The improvement of a fail-safe counter for low-speed detection required a simple calculation of the circuit without any use of CPUs. These diagnoses were regarded as the frequency domain and time domain. When the motor speed became lower than the predetermined speed and there were no parts of the digital counter circuit malfunction, the dynamic signals with the low-pass frequency would be provided to the filter and the DC signal would eventually be the output, as the low-speed detection results displayed a fail-safe manner. These have been revealed by the FMEAs of the fail-safe counter, including the failure modes.