Phase noise performance of fully differential sub-harmonic injection-locked PLL

摘要

A fully differential sub-harmonic injection-locked phase-locked loop (PLL) that achieves improved levels of phase noise performance through the incorporation of injection locking and fully differential architecture is presented. Details concerning the design of each building block are given and the corresponding simulation results are presented. The system level architecture exploration is introduced together with the phase noise analysis. A physical implementation of the proposed design using a standard 0.5 ;C;m SiGe BiCMOS process is also presented as a case study in order to prove the functionality as well as the overall performance. Phase noise improvement is 20 dB at 1 kHz when a sub-harmonic of the free-running oscillation frequency at 2.5 GHz with a 215 dBm power level is injected.