Data interface key to future apps

摘要

By the year 2005, applications such as games, high-end graphics and routers will require chip-to-chip speeds of 10 to 100 Gbytes/second, while IC I/O-related cost and power consumption must remain roughly at the levels we see today. Unfortunately, incremental developments of today's technologies would be unable to achieve that performance/cost ratio. Today we can achieve 4.25-Gbyte/s data rates using a 128-bit-wide 266-MHz SSTLbus with double-data-rate SDRAM. Increasing that to 34.2 Gbytes/s, however, would require a 512-bit bus operating at 533 MHz. Obviously, a new interface is needed-one that offers a quantum leap in performance while staying within low-cost, high-volume manufacturing constraints.