COT design path eyes interconnect crunch

摘要

Designers of internetworking products face a number of challenges that dictate choices in chip design methodologies. The Internet is growing slightly faster than the formidable Moore's Law. Packet-processing requirements get more intense every year as the market demands more features. And customers increasingly want solutions that are programmable rather than hard-coded so that hardware can have a longer useful life. Beyond these requirements, products in this space must meet such requirements as stability, reliability, high availability, scalability, density and low total cost of ownership. As a result, to stay competitive in this marketplace, design teams must do much more than just ride the wave of new silicon process technology. To maintain leadership, design teams are designing chips that now represent the bleeding edge in design complexity. Some chips of more than 250 million transistors, running at 400 MHz or more, have been fabricated. Still bigger and faster chips are under design.