IP reuse simplifies SoC design, verification

摘要

Larger, more-complex digital designs demand inventive techniques and tools that simplify the design and verification process. This is a response to both design complexity challenges and the new opportunities of increased silicon real estate. For example, at this year's Design Automation Conference, Gary Smith of Dataquest observed that the advent of 65-nanome-ter processes marked the first time that system developers were unable to use all of the available design gates. This gap between fabrication and design potential has been recognized by the EDA industry, which has been hard at work on various strategies to close it. One of the most promising is the automated integration of intellectual property (IP) using a platform-based design strategy.