SOC TEST SYSTEM SPEDS DESIGN VERIFICATION, CUTS TEST COST

摘要

As system-on-a-chip complexity in-creases, testing the millions of gates that get integrated on the chip has become an ever more challenging and more expensive task. On-chip test support logic and built-in self-test (BIST) circuits jhave been developed to handle the design-for-test (DFT) methodologies that are now almost mandatory for new designs. Such test capabilities are needed because many functions embedded in the complex chips are unreachable from external pins, or because the time and cost of the test systems to access the blocks makes the testing very slow and very expensive. Typically, when the first system-on-a-chip (SoC) comes off the manu- facturing line, exten- sive testing is per- formed to ensure that the DFT circuits func-tion as desired. But the multimillion dollar test systems that are often required to perform the analysis are usually kept very busy on the production test floor. Finding time to perform engineering verification frequently means staying overnight at the factory to get some time on the large production tester. On top of that, these "big iron" test systems aren't optimized to handle the internal test structures inside the SoCs.