Supply-Voltage Scaling Close to the Fundamental Limit Under Process Variations in Nanometer Technologies

摘要

The fundamental limit on the minimum allowable supply voltage of a complementary metal–oxide–semiconductor (CMOS) logic gate for binary signal discrimination is $V_{{rm dd}, min} cong hbox{2}(lnhbox{2})kT/q$. With the theoretical analysis of our proposed circuit technique, we demonstrate an ultralow-voltage operation with two 1000-stage inverter chains fabricated in 130- and 65-nm technologies, which can work all the way down to a supply voltage of 50 and 60 mV (with output swings of 42 and 43 mV), respectively, and are close to the fundamental limit of logic operation. For the first time, we present a measured minimum dynamic-switching energy of 21.3 aJ/cycle. This is accomplished by modulating the effective $beta$-ratio to balance the p-channel and n-channel MOS transistors in strength, enabling the operation of standard CMOS logic at ultralow voltages. We also discuss 41-stage ring oscillators, which clearly show the existence of different optimal $beta$-ratios in different regions of operation in terms of performance and robustness under process variations.