Hitachi SuperH Series

摘要

The SuperH Series comprises the SH-1, SH-2, SH-3, SH-4, SH-5 and variations of the hybrid RISC SH-DSP series of RISC μPs, μCs, and ASIC cores. The SH-1, -2, and -3 employ a fetch, decode, execute, memory-access, and write-back-to-register pipeline. Hitachi built the devices around 25 32-bit registers that you access using load/store instructions. These registers comprise 16 general registers, five control registers, and four system registers. (The SH-3 has eight 32-bit shadow registers for context switching.) Depending on the chip, the interrupt latency can be as low as seven clock cycles.