Altera Nios soft-core processor

摘要

Nios is a soft-core CPU that Altera designed from scratch to fit into its Apex FPGA devices. Altera designed Nios' architecture and instruction set with the goals of having a "no-physical-wires" interface to user logic, a modern, pipelined RISC architecture, and a compiler-friendly instruction set. Other goals were to yield reasonable performance of 33 to 50 MHz and the ability to execute one instruction per clock.