Alternative approaches to SOC test

摘要

When you purchase an independently developed IP (intellectual-property) core, it is usually unclear how well it conforms to DFT (design-for-test) rules and, hence, what fault coverage is possible. Even when designers strive to follow DFT rules for new functions, it is sometimes impossible to comply, due to design constraints and requirements. Sometimes, the synthesis process produces constructs that inherently violate DFT rules. To be successful, designers must care-fully choose the IP they purchase with regard to ease of test integration and the degree to which DFT violations may affect the overall fault coverage for the SOC design. They must also use appropriate synthesis constraints to avoid DFT violations. Alternatively, designers may consider new architectural approaches to the problem so that the underlying SOC/ASIC architecture incorporates provisions that remove the test burden from them.