Dynamic frequency scaling optimizes SOC performance

摘要

Most IC designs involve engineering trade-offs. For example, when determining the operating frequency of an SOC (system on chip), the system architect has to consider how the frequency will impact design attributes, such as power consumption and die size. Another common consideration is the timing of a "key" path that significantly affects application or benchmark performance. Sometimes, despite all efforts, the worst-case delay through this path does not fit neatly into an integer number of clock periods. In this case, the architect needs to either accept the slack and any corresponding extra wait states in the path or, if the performance of this key path is of overriding importance, reduce the operating frequency of the SOC so that it requires fewer wait states and optimizes the path timing.