MIPS Technologies' multithreaded, multiprocessor, coherent-processing MIPS32 1004K licensable-IP (intellectual-property) platform supports as many as four single- or double-threaded processor cores that connect through a coherence manager. The nine-stage-pipeline architecture supports a worst-case 800-MHz-base-core operating frequency in a 65-nm TSMC (Taiwan Semiconductor Manufacturing Co, www.tsmc.com) general-purpose process. The architecture implements a dual-core, dual-threaded configuration for a total of four threads. The architecture also has 32-kbyte caches for each core, a coherence manager, and a global-interrupt controller. The devices include 1004Kc integer and 1004Kf floating- point versions of the core, and they both support Revision 1 of the MIPS32 DSP ASE (application-specific extension).
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