Phasor-based fault location challenges and solutions for transmission lines equipped with high-speed time-domain protective relays

摘要

This paper presents a study on the performance of phasor-based fault location methods under reduced fault period conditions. Such a scenario can arise in lines equipped with high-speed circuit breakers (CBs) and time domain protective relays, so that the fault can be eliminated even before it reaches its steady-state. Considering this context, challenging scenarios that may arise during phasor-based fault location procedures are firstly addressed, and then statistical approaches for fault location estimation sample processing are investigated, evaluating their advantages and limitations. Initially, Alternative Transients Program (ATP) fault simulations are carried out to generate realistic fault records, which are played back into actual micro-processed relays equipped with both high-speed time-domain protection functions and phasor-based fault location algorithms. Finally, by means of tests using a Real-Time Digital Simulator (RTDSTM) and an actual Digital Fault Recorder (DFR), different procedures to analyze phasor-based fault location data are assessed. The obtained results show the statistical processing of fault location estimations can improve existing fault location procedures in some cases, but not completely solving the problem if CBs come to be faster than those in the present technology.