A Home-type (H-type) Cascaded Multilevel Inverter with Reduced Device Count: Analysis and Implementation

摘要

Multilevel inverter (MLI) is increasingly recognized as a low distorted wave synthesizing power converter built using recent power semiconductor devices. However, MLIs suffer from the requirement of higher device count. In this paper, a 15-level Home-type (H-type) inverter topology is proposed to address this concern. The H-type inverter topology is cascaded to synthesize a higher number of levels in output voltage. Voltage ratings of the dc sources are designed to generate a large number of uniform steps in output voltage. Analysis of the proposed method is presented for required number of switches, dc voltage sources, driver circuits and blocking voltage of switches. Comparative study demonstrates that the suggested topology requires reduced device count compared to the similar topologies reported in the literature. Simulation and experimental studies have been carried out to validate the performance of proposed MLI topology.