The thermal stress induced by annealing the Cu filling of through-silicon vias (TSVs) requires further study as it can inhibit the performance of semiconductor devices. This paper reports the filling behavior of TSVs prepared using direct current and pulse current Cu electrodeposition with and without pre-annealing. The thermal extrusion of Cu inside the TSVs was studied by observing the extrusion behavior after annealing and the changes in grain orientation using scanning electron microscopy (SEM) and electron backscatter diffraction (EBSD). The bottom-up filling rate achieved by the direct current approach decreased because the current was used both to fill the TSV and to grow bump defects on the top surface of the wafer. On the other hand, pulse current electrodeposition yielded an improved TSV bottom-up filling rate and no bump defects, which is attributable to strong suppression and a thin diffusion layer. Moreover, Cu deposited with a pulse current exhibited lesser thermal extrusion, which was attributed to the formation of nanotwins and a change in the grain orientation from random to (101). Based on the results, thermal extrusion of the total area of the TSVs could be obtained by pulse current electrodeposition with pre-annealing.
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