A switched capacitor converter (SCC) is a kind of inductor-less power converters. The fact that the SCC has no magnetic components leads to reduce the size as well as electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems. Until now, many types of SCCs have been suggested. Among those topologies, single type topologies have room to improve their power efficiency. A solution is to merge two single topologies and to design a parallel topology. In previous researches, the parallel SCC topologies were analyzed, neglecting either their slow switch limit (SSL) or fast switch limit (FSL). In this study, applying a circuit model including both SSL and FSL, the output impedance of the parallel SCC topology is derived to improve the accuracy of the modeled output impedance. The theoretical analysis is verified by the simulation results. This study can provide future circuit designers with more accurate characterization of the parallel SCC topology.
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