A Novel Approach For Error Detection And Correction Using Prefix-Adders

摘要

The variable latency speculative Han-Carlson adder is a newly proposed adder to perform high speed arithmetic operations. Han-Carlson adder gives accurate results with error detection when compared to other adders like Kogge-Stone adder. In this paper, number of parallel prefix adders can be sub divided into number of stages and perform arithmetic operations. By using the Xilinx 14.2 software, the design of Kogge-Stone adder and Han-Carlson adder is developed. This paper focuses on the implementation and simulation of 8-bit, 16-bit Kogge-stone adder and Han- Carlson adder based on Verilog code and compared for their performance in Xilinx. When compared to other adders the delay performance for Han Carlson adder is less and it reduces the complexity. It is concluded that the proposed adder is better in terms of computational delay. By using Brent ?Kung and Kogge-stone adder the parallel prefix Han-Carlson adder also be proposed.