The trend in VLSI and system design is moving away from high speed to low power due to the rapid growth in the portable consumer electronics market. The technology evolution of deep submicron (DSM) will be able to manage the needs and demands of future computing world. A rapid growth of future computing have led to challenges of very deep submicron (DSM) regime. Here, the leakage power plays a major contributor to the total power dissipation involved in the circuit as the threshold voltage becomes small while we reduce the operating supply voltage. We present some techniques to reduce the power dissipation involved while interconnecting logic blocks in the Field Programmable Gate Arrays (FPGAs). The interconnections or connectivity among logic blocks are done by routing switches. We use pass-transistor logic, transmission logic and multiplexers for the construction of these routing switches. We present a technique which has both sleep mode in which the leakage power is reduced and low-power mode in which the dynamic power is reduced. These models are built by using Electronic Design Automation (EDA) tools like DSCH (Digital Schematic) and Microwind layout tools using BSIM4 MOSFET model in 60 nm technology. Results show that the pass-transistor approach is having low power consumption . The leakage and dynamic power are also reduced by the circuit which has the programmability option to change sleep mode and low-power mode.
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