Low Quantum Cost Realization of Reversible Binary-Coded-Decimal Adder

摘要

The ability of reversible design to reduce power consumption in designing digital circuits compared to the traditional logic design has been gaining much attention in recent decades. Also, because of the attention gained by the decimal arithmetic in the application of commercial, internet-based systems, etc, an approach to design the reversible binary-coded-decimal adder is proposed and carried out in this paper. Proper selection and arrangements of the gates with parallel implementation have been able the proposed design to show improvements in the reversible performance parameters. The proposed design shows the most efficient design with at least 10% improvements of quantum cost compared with existing counterparts found in the literature. Furthermore, the proposed design is mapped into the quantum equivalent circuit using RCViewer+ tool.