A Novel Hardware Efficient Reconfigurable 32-Bit Arithmetic Unit for Binary, BCD and Floating Point Operands

摘要

This paper provides the details for novel adder/subtractor arithmetic unit that combines Binary, Binary Code Decimal (BCD) and single precision Binary floating point operations in a single structure. The unit is able to perform effective addition-subtraction operations on unsigned, sign-magnitude, and various complement representations. The design is runtime reconfigurable or can be implemented in ASIC as a runtime configurable unit and maximum utilization of hardware resource are the feature of the architecture. All the subunits have been designed to work with least delay. The modified unit and base unit were synthesized for 4vfx60ff672-12 Xilinx Virtex 4 FPGA for comparison. The proposed design has 8.9ns delay and achieve throughput of 112.3 MOPS using only 2% of the available hardware resources of the targeted FPGA. Under the assumption that significant part of the hardware in the proposed structure is shared by the different operation reconfigurable platforms with partial reconfiguration become an interesting target.