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首页> 外文期刊>IEICE transactions on information and systems >Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh
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Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

机译:用于使用非结构化网格的流体动力学计算可重新配置的无序系统

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摘要

Computational fluid dynamics (CFD) is an important tool for designing aircraft components. FaSTAR (Fast Aerodynamics Routines) is one of the most recent CFD packages and has various subroutines. However, its irregular and complicated data structure makes it difficult to execute FaSTAR on parallel machines due to memory access problem. The use of a reconfigurable platform based on field programmable gate arrays (FPGAs) is a promising approach to accelerating memory-bottlenecked applications like FaSTAR. However, even with hardware execution, a large number of pipeline stalls can occur due to read-after-write (RAW) data hazards. Moreover, it is difficult to predict when such stalls will occur because of the unstructured mesh used in FaSTAR. To eliminate this problem, we developed an out-of-order mechanism for permuting the data order so as to prevent RAW hazards. It uses an execution monitor and a wait buffer. The former identifies the state of the computation units, and the latter temporarily stores data to be processed in the computation units. This out-of-order mechanism can be applied to various types of computations with data dependency by changing the number of execution monitors and wait buffers in accordance with the equations used in the target computation. An out-of-order system can be reconfigured by automatic changing of the parameters. Application of the proposed mechanism to five subroutines in FaSTAR showed that its use reduces the number of stalls to less than 1% compared to without the mechanism. In-order execution was speeded up 2.6-fold and software execution was speeded up 2.9-fold using an Intel Core 2 Duo processor with a reasonable amount of overhead.
机译:计算流体动力学(CFD)是设计飞机部件的重要工具。 FASTAR(快速空气动力学例程)是最近的CFD包之一,并且具有各种子程序。然而,其不规则和复杂的数据结构使得由于内存访问问题而难以在并联机器上执行快速。基于现场可编程门阵列(FPGA)的可重构平台的使用是一种有希望的方法,可以加速像快速的内存瓶颈的应用。但是,即使使用硬件执行,由于读写写入(RAW)数据危险,可能会发生大量管道档位。而且,难以预测,因为由于在快速中使用的非结构化网格而发生这种档位。为了消除这个问题,我们开发了一种禁用数据顺序的超出机制,以防止原始危险。它使用执行监视器和等待缓冲区。前者识别计算单元的状态,并且后者临时存储要在计算单元中处理的数据。通过根据目标计算中使用的等式来改变执行监视器数和等待缓冲器,可以应用于具有数据依赖性的各种类型的计算。可以通过自动更改参数来重新配置无序系统。将提出的机制应用于FASTAR中的五个子程序表明,与没有机制相比,其使用将摊位数减少至小于1%。按顺序执行加速2.6倍,软件执行使用英特尔核心2 Duo处理器加速2.9倍,具有合理的开销。

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