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首页> 外文期刊>Sensors >Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference
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Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

机译:超低功率高温和辐射硬互补金属氧化物半导体(CMOS)绝缘体上硅(SOI)电压基准

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This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.
机译:本文提出了一种超低功耗CMOS电压基准电路,该电路在生物医学极端条件下(例如高温和高总电离剂量(TID)辐射)具有鲁棒性。为了实现这样的性能,参考电压采用合适的130 nm绝缘体上硅(SOI)工业技术进行设计,并经过优化以在晶体管的亚阈值范围内工作。设计仿真是在−40–200°C的温度范围内以及不同工艺角进行的。使用包括TID效应(例如迁移率和阈值电压降级)在内的自定义模型参数模拟了辐射的鲁棒性。所提议的电路已经过测试,可以达到高总辐射剂量,即在三种不同温度(室温,100°C和200°C)下执行1 Mrad(Si)的测试。参考电压V REF 的最大漂移取决于所考虑的温度和辐射剂量。但是,它仍然低于1.5 V平均值的10%。在2.5 V电源电压下,典型功耗在室温下约为20μW,而在200°C的高温下仅为75μW。为了了解高总电离剂量和温度对这种基准电压的影响,在不同条件下提取了所用SOI MOSFET的阈值电压。 V REF 和功耗随温度和辐射剂量的变化可以用固定氧化物电荷和界面态建立之间的不同平衡来解释。包括垫环在内的总占地面积小于0.09 mm 2

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