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An Efficient Hardware-Based Fault-Tolerant Method for SMS4

机译:SMS4的一种基于硬件的高效容错方法

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The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.
机译:SMS4密码系统已在无线局域网身份验证和隐私基础结构(WAPI)标准中使用,用于在中国提供数据机密性。到目前为止,可靠性尚未被视为原始版本的主要目标。但是,无论是自然还是恶意注入的故障,加密/解密过程中的单个故障都可以完全改变密码系统的结果。在本文中,我们为SMS4密码系统提出了一种低成本的结构无关的故障检测方案,该方案能够执行在线错误检测,并且能够以100%的覆盖率检测单个位故障或奇数个多位故障。最后,在Virtex-7系列FPGA平台上对提出的技术进行了验证,以分析其功耗,开销和时间延迟。运行具有0.735ns检测延迟的SMS4密码系统的容错方案,只需要85个占用的Slices和8.72mW。与以前的方案相比,我们的新方案增加了最小冗余,以增强密码系统的可靠性并实现更好的性能。

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