Finger Vein &Texture Recognization Using Score Level Fusion And 2-D Gabor Filter For Human Identification

摘要

In this paper, an efficient method for high speed hardware implementation of AES algorithm is presented. So far, many implementations of AES have been proposed, for various goals that effect the Sub Byte transformation in various ways. These methods of implementation are based on combinational logic and are done in polynomial bases. In the proposed architecture, it is done by using composite field arithmetic in normal bases. In addition, efficient key expansion architecture suitable for 6 sub pipelined round units is also presented. These designs were described using VerilogHDL, simulated using Modelsim