Design &Implementation of I2C Master Controller Interfaced With RAM Using VHDL

摘要

In most of the applications, the physical systems require a real-time operation to interface high speed constraints. In most of the applications, the physical systems require a real-time operation to interface high speed constraints. The Inter Integrated Circuits (I²C) is a 2-wireed communication bus. Physically, it consists of 2 active wires: SDA (Serial Data), SCL (Serial Clock) and a ground connection. All I²C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I²C-bus. This paper focuses on the software implementation for I²C Driver and its interfacing with RAM. Specifically, this paper describes in detail an I²C Master connected to I ²C Slave using an I²C bus. The I²C protocol was given by Philips Semiconductors for faster devices to communicate with slower devices and each other without data loss. The complete module is designed in VHDL and simulated in Xilinx ISE 14.5.