Design of On Chip Bus Using Core Centric Protocol

摘要

As more and more IP cores are integrated into an SOC design, the communication flow between IP cores has increased drastically and the efficiency of the on-chip bus has become a dominant factor for the performance of a system. The on-chip bus design can be divided into two parts, namely the interface and the internal architecture of the bus. In this work the well-defined interface standard is adopted, the Open Core Protocol (OCP), and focus on the design of the internal bus architecture. The Open Core Protocol (OCP) is a core centric protocol which defines a high- performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs for SOC designs. Main property of OCP is that it can be configured with respect to the application required. The OCP is chosen because of its advanced supporting features such as configurable sideband control signaling and test harness signals, when compared to other core protocols