28nm FPGA based Power Optimized UART Design using HSTL I/O Standards

摘要

UART abbreviated as Universal Asynchronous Receiver Transmitter is one of the essential element of communication system. It is being mostly used when there is a short-distance, between computer and peripherals. Whenever there is low-cost data exchange or the speed required for transmission is not high, UART’s are also being used there. For the achievement of compact, stable and reliable data transmission, the implementation of UART with VHDL language can be integrated into FPGA. The Total power and Junction temperature of UART have been analyzed in the following paper when it is operating on different I/O standards of HSTL (HIGH SPEED TRANSCEIVER LOGIC) logic family and different range of frequencies from 1 GHz to 46 GHz. Analysis have also been done for two different 28nm FPGA’s which helps to compare the total power reduction at two different FPGA technology so that the best suited FPGA for UART design consuming the least could be discovered. After analysis, it has been concluded that 91.96% of the total power can be saved in the case Kintex-7 and 91.98% of total power can be preserved in case of Artix-7 by operating the design at a frequency of 1 GHz. On the other hand the Junction temperature has been reduced to 11.84% in case of Kintex-7 and it has been reduced to 15.28% in case of Artix-7.