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首页> 外文期刊>Universal Journal of Electrical and Electronic Engineering >Towards Interference Alignment for Distributed Large-Scale MIMO Hardware Architecture and Implementation
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Towards Interference Alignment for Distributed Large-Scale MIMO Hardware Architecture and Implementation

机译:面向分布式大规模MIMO硬件架构的干扰对准和实现

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Massive MIMO or Large Scale MIMO is a promising solution for achieving superior data rates in 5G communication systems. However it has limitation in term of scalability and coverage for users that has highly spatial separation. Distributed massive MIMO is expected to enhance these drawbacks. One main problem arises in this scheme is the MIMO interference channel conditon that can be coped by interference alignment algorithm. The main consideration for interference alignment algorithm in distributed Massive MIMO is to achieve low complexity precoding to eliminate interference channel condition and to design efficient hardware architecture for its implementation. Previous research regarding IA for Distributed Massive MIMO indicates that the complexity issues is still not widely discussed. This paper proposed the low complexity IA scheme for large scale MIMO system based on limited interferer and the implementation of low cost interference alignment and wireless synchronization for distributed MIMO using software defined radio hardware. From the simulation result it is shown that limited interferer IA algorithm achieve acceptable BER performance, i.e. in order of 10~(-3). The hardware implementation of the IA precoding matrix computation is also discussed and base on the experiment it is show that the proposed algorithm and architecture achieved higher hardware performance compared to the linear IA.
机译:大规模MIMO或大规模MIMO是在5G通信系统中实现卓越数据速率的有前途的解决方案。然而,对于高度空间分离的用户而言,在可伸缩性和覆盖范围方面存在局限性。分布式大规模MIMO有望增强这些缺点。该方案中出现的一个主要问题是可以通过干扰对准算法来应对的MIMO干扰信道条件。分布式Massive MIMO中干扰对准算法的主要考虑因素是实现低复杂度的预编码,以消除干扰信道条件,并设计高效的硬件架构以实现其实现。关于分布式大规模MIMO的IA的先前研究表明,复杂性问题仍未得到广泛讨论。本文提出了一种基于有限干扰源的大规模MIMO系统的低复杂度IA方案,并通过软件无线电硬件实现了分布式MIMO的低成本干扰对准和无线同步的实现。从仿真结果表明,有限的干扰IA算法达到了可接受的BER性能,即大约为10(-3)。还讨论了IA预编码矩阵计算的硬件实现,并在实验的基础上表明,与线性IA相比,该算法和体系结构具有更高的硬件性能。

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