Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

摘要

Reconfigurable Computers (RCs) with hardware (FPGA) co-processorscan achieve significant performance improvement compared withtraditional microprocessor (μP)-based computers for manyscientific applications. The potential amount of speedup depends on the intrinsic parallelism of the target applicationas well as the characteristics of the target platform. In this work,we use image processing applications as a case study to demonstratehow hardware designs are parameterized by the co-processorarchitecture, particularly the data I/O, i.e., the local memory of the FPGA device and the interconnectbetween the FPGA and theμP. The local memory has to be used by applications that access data randomly. A typical casebelonging to this category is image registration. On the other hand,an application such as edge detection can directly read data through theinterconnect in a sequential fashion. Two different algorithms ofimage registration, the exhaustive search algorithm and the DiscreteWavelet Transform (DWT)-based search algorithm, are implemented onhardware, i.e., Xilinx Vertex-IIPro 50 on the Cray XD1 reconfigurable computer. Theperformance improvements of hardware implementations are10×and2×, respectively. Regarding the category of applications thatdirectly access the interconnect, the hardware implementation of Canny edge detection can achieve544×speedup.