A Floating Point Multiplier based FPGA Synthesis for Neural Networks Enhancement

摘要

FPGA (Field Programmable Gate Array) implementation of Artificial Neural Networks (ANNs) calls for multipliers of various word lengths. In this paper, a new approach for designing a Floating Point Multiplier (FPM) is developed and tested using VHDL. With VHDL (Very High Description Language) analyzer and logic synthesis software, hardware prototypes could be implemented in FPGA.