Efficient VLSI Architecture for 1-D 9/7 Discrete Wavelet Transform

摘要

Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it features onchip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient 1D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization efficiency.