Design of Improved Routers for Network on Chip

摘要

This paper presents an improved router design for network on chip (NoC). Networkonchip provides large interconnection schemes for complex SoC design. Parameters like power, delay, area, through put influence the performance of NoC. Here power delay product (PDP) is analyzed, which are of prime importance with reference to hardware implementation. In router designing the power consumption is basically due to the buffers and the crossbar. The proposed routers are designed at 180nm technology and we compare the performance with baseline router and virtual channel router on the same platform. The proposed router using dual crossbar achieves 25.5% and 60.88% lower PDP, while proposed router using multicrossbar achieves 37.91% and 61.92% lower PDP, as compared to the baseline router and virtual channel router respectively.