FPGA Implementation of Area Efficient and High Throughput 2D DTCWTArchitecture with Pipelined Scheme

摘要

Dual Tree Complex Discrete Wavelet Transform (DTCWT) decomposes input image intoapproximation and six detail sub-bands using row and column processing filter banks. Each filter comprisingof 10 coefficients requires multipliers and adders that are twice larger than that of discrete wavelet transformcomputation. In this study, the computation complexity in DTCWT computation is reduced by considering theredundancy in filter coefficients. A multiplexer-demultiplexer based logic is designed to reduce the number offilters by 75%, a pipeline architecture is designed to reduce the number multipliers by 60% as compared withconventional DTCWT architecture. The designed architecture implemented on FPGA and the design operatesat frequency of >200 MHz.