Iterative channel decoders such as Turbo-Code and LDPC decoders showexceptional performance and therefore they are a part of many wirelesscommunication receivers nowadays. These decoders require a soft input, i.e.,the logarithmic likelihood ratio (LLR) of the received bits with a typicalquantization of 4 to 6 bits. For computing the LLR values from a receivedcomplex symbol, a soft demapper is employed in the receiver.The implementation cost of traditional soft-output demapping methods isrelatively large in high order modulation systems, and therefore lowcomplexity demapping algorithms are indispensable in low power receivers. Inthe presence of multiple wireless communication standards where each standarddefines multiple modulation schemes, there is a need to have an efficientdemapper architecture covering all the flexibility requirements of thesestandards. Another challenge associated with hardware implementation of thedemapper is to achieve a very high throughput in double iterative systems,for instance, MIMO and Code-Aided Synchronization.In this paper, we present a comprehensive communication and hardwareperformance evaluation of low complexity soft-output demapping algorithms toselect the best algorithm for implementation. The main goal of this work isto design a high throughput, flexible, and area efficient architecture. Wedescribe architectures to execute the investigated algorithms. We implementthese architectures on a FPGA device to evaluate their hardware performance.The work has resulted in a hardware architecture based on the figured outbest low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficientarchitecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.
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