Forward error correction based on trellises has been widely adopted forconvolutional codes. Because of their efficiency, they have also gained a lotof interest from a theoretic and algorithm point of view for the decoding ofblock codes. In this paper we present for the first time hardwarearchitectures and implementations for trellis decoding of block codes. A keyfeature is the use of a sophisticated permutation network, the Banyannetwork, to implement the time varying structure of the trellis. We haveimplemented the Viterbi and the max-log-MAP algorithm in different foldedversions on a Xilinx Virtex 6 FPGA.
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