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FPGA Implementation of a Simple 3D Graphics Pipeline

机译:简单3D图形管线的FPGA实现

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Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation) and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing).
机译:如今,通常在标准或图形处理器上实现用于计算3D项目的常规方法。这些设备的性能尤其受到所用体系结构的限制,所使用的体系结构在某种程度上以顺序的方式起作用。在本文中,我们描述了一个利用并行计算对线框3D模型进行简单投影的项目。该算法针对基于FPGA的实现进行了优化。在VHDL中,使用几个基本IP核(尤其是用于计算三角函数的核对)来描述数字逻辑的设计。实施的算法允许模型在两个轴(方位角和仰角)上平滑旋转,并可以改变视角。在FPGA Xilinx Spartan-6开发板上进行的测试已实现了超过5000fps的实时渲染。在本文的结论中,我们讨论了通过使用HPC(高性能计算)来增加图形应用程序中的计算输出的其他可能性。

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