Simulation results of the electrical performance at 1 GBits/sec of a number of different off-chip interconnectionarchitectures are presented with emphasis given to the dependence of crosstalk and signaldelay on the geometries and dielectric constants of the insulating layers as well as on the widths andseparations of the conductors. The results indicate that signal delay and crosstalk may be reduced byusing lowεrvalues for the dielectrics and that crosstalk may be also reduced by reducing the conductor-to-ground wire separation which simultaneously neutralises the role ofεrvalue on crosstalk and lineimpedance.
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