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Multi-objective optimization and visualization for analog design automation

机译:模拟设计自动化的多目标优化和可视化

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Abstract The automated design of analog and mixed-signal circuits is a well-known subject of increasing technical and economical significance, e.g., sensory circuits for internet of things, cyber-physical systems, and Industry?4.0.The demand for rapid solution achievement under constraints, as, e.g., robustness, in established and emerging technologies as well as the migration between technologies gives incentive to automation activities. Existing approaches and tools still show improvement potential with regard to multi-variate modeling, efficient and multi-objective optimization, as well as transparence and user interaction options during the design. This paper presents new approaches applied within an emerging design environment, denoted as ABSYNTH, with an evolving self-learning architecture for efficient hierarchical optimization in a cascade, which includes function approximators and simulators trained by proven evolutionary optimization algorithms, as well as a novel domain-specific visualization of the optimization space and the trajectory of the design process. Nominal schematic-level sizing of the commonly used Miller, buffer, and folded-cascode amplifier circuits has been studied with our approach. For Miller, buffer, and folded-cascode, a cascade of harmony search and particle swarm optimization on SVR, ngspice, and cadence simulators was found to be roughly 4 times, 2.5 times, and 2.5 times faster, respectively, than the flat approach with equal or better results. In future work, we will improve the approach by including more demanding circuits, statistical deviations, circuit breeding, advanced optimization, and layout generation.
机译:摘要模拟和混合信号电路的自动化设计是一个众所周知的主题,具有越来越高的技术和经济意义,例如,用于物联网,网络物理系统和工业4.0的传感电路。现有技术和新兴技术的局限性(例如鲁棒性)以及技术之间的迁移为自动化活动提供了动力。现有的方法和工具在多变量建模,高效和多目标优化以及设计过程中的透明度和用户交互选项方面仍显示出改进的潜力。本文介绍了在新兴设计环境(称为ABSYNTH)中应用的新方法,该方法具有不断发展的自学习体系结构,可在级联中进行有效的分层优化,其中包括通过经过验证的进化优化算法训练的函数逼近器和模拟器,以及新颖的领域优化空间和设计过程轨迹的特定可视化。我们的方法已经研究了常用的Miller,缓冲器和折叠共源共栅放大器电路的标称原理图尺寸。对于Miller,缓冲区和折叠式共源共栅,在SVR,ngspice和cadence模拟器上进行的和谐搜索和粒子群优化级联分别比平面方法快4倍,2.5倍和2.5倍。等于或更好的结果。在未来的工作中,我们将通过包含更多要求苛刻的电路,统计偏差,电路选育,高级优化和布局生成来改进方法。

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