High Speed Low Power CMOS Domino or Gate Design in 16nm Technology

摘要

Dynamic logic circuits provide more compact designs with faster switching speeds and lowpower consumption compared with the other CMOS design styles. This paper proposes a widefan-in circuit with increased switching speed and noise immunity. Speed is achieved by quicklyremoving the charge on the dynamic node during evaluation phase, compared to the othercircuits. The design also offers very less Power Delay Product (PDP). The design is exercisedfor 20% variation in supply voltage.