Modeling and Analysis of Parametric Yield under Power and Performance Constraints

摘要

CONTINUED SCALING of device dimensions, combined with shrinking threshold voltages, has resulted in an exponential rise in IC power dissipation. This increase is primarily due to leakage, which is emerging as a significant portion of total power consumption. Kao, Narendra, and Chandrakasan estimate that subthreshold leakage power will account for more than 50percent of total power for portable applications developed for the 65-nm technology node. In future technologies, aggressive scaling of oxide thickness will lead to significant gate oxide tunneling current, further aggravating the leakage problem. Across successive technology generations, subthreshold leakage increases by about 5 times, and gate leakage can increase by as much as 30 times.