Building meaningful timed models of closed-loop DES for verification purposes

摘要

Formal verification methods require that a model of the system to analyze, in the form of a network of automata for instance, be built previously. Every evolution of this formal model must represent a real evolution of the modeled system; if the model contains indeed spurious evolutions, meaningless states, which do not correspond to physically possible states, can be reached and the verification results are surely not trustworthy. This paper focuses on construction of the formal model of a closed-loop system which can be represented as a Discrete Event System (DES) and where all evolutions and states are meaningful w.r.t. to the real system behavior. A closed-loop system is composed of a physical system to control, named plant, and a controller. A modular approach to build the plant model is presented in the first part of the paper; to prevent from meaningless evolutions and states in this model, a solution based on the concept of urgent edges is proposed and exemplified. Then, construction of the formal model of the closed-loop system is addressed; it is shown that restriction of the evolutions of this model to the only meaningful ones can be easily achieved by introducing variables that represent the modification of the inputs of the logic controller and the stability condition of the control specification.