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Low-complexity receiver algorithms for the Grand-Alliance VSB HDTV system

机译:Grand-Alliance VSB HDTV系统的低复杂度接收机算法

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We develop and simulate algorithms required for the front end of the baseband Grand-Alliance high-definition television (G-A HDTV) receiver. This includes noncoherent and coherent automatic gain controls, IF-FPLL polarity detection, segment synchronization and symbol timing recovery. Especially, we propose a simple polarity detection algorithm that resolves the bi-stability of the IF-FPLL unit used in the G-A, HDTV receiver and a segment synchronization algorithm that can be implemented with reduced complexity compared to that proposed by Sgrignoli, Bretl and Citta (see ibid., vol.41, no.3, p.367, 1995) and Bretl, Sgrignoli and Snopko (see ibid., vol.41, no.3, p.773, 1995). Computer simulation results show that the overall receiver design gives satisfactory performance under AWGN, multipath fading and timing drift. Finite bit precision simulations are also performed to determine the proper bit precisions required for each of the functional blocks for circuit implementation. The practical operation of the design is verified via HDL construction and simulation.
机译:我们开发并仿真基带Grand-Alliance高清晰度电视(G-A HDTV)接收机前端所需的算法。这包括非相干和相干自动增益控制,IF-FPLL极性检测,段同步和符号定时恢复。特别是,我们提出了一种简单的极性检测算法,该算法可解决GA,HDTV接收器中使用的IF-FPLL单元的双稳定性,以及一种与Sgrignoli,Brert和Citta相比可以降低复杂度的分段同步算法。 (参见同上,第41卷,第3期,第367页,1995年)和Bretl,Sgrignoli和Snopko(参见同上,第41卷,第3期,第773页,1995年)。计算机仿真结果表明,整个接收机设计在AWGN,多径衰落和定时漂移下均具有令人满意的性能。还执行有限的位精度仿真,以确定电路实现的每个功能块所需的合适位精度。通过HDL的构建和仿真验证了设计的实际操作。

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