A video decoder with an efficient block-level-pipeline controller scheme for MPEG-2 MP@ML is presented. The architecture in most of the reported literature for MPEG-2 MP@ML video uses a 64-bit bus and a complex bus arbitration scheme to communicate with the external DRAM, the display, and the incoming FIFO. Our design imposes a certain order in the DRAM access by various processing units instead of allowing any processing unit within the decoder to request bus access arbitrarily. This efficient DRAM accessing order allows us to reduce bus width from 64 bits to 32 bits, without significantly increasing the embedded buffer sizes, and still meet the requirements for MPEG-2 MP@ML real-time decoding. The bus arbitration algorithm is also simple, allowing for a less complex controller design.
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