Error Floor Estimation of QC-LDPC Coded Modulation With Importance Sampling

摘要

This letter presents a low-complexity error floors estimation method for bit-interleaved coded modulation with quasi-cyclic low-density parity-check (LDPC) codes. Using surrogate bit-channels (SBCs) as hypothetic equivalent channels, the importance sampling method based on the stable trapping sets is applied to evaluate the error floors. It is shown that the error floors of bit-interleaved coded modulation systems can be effectively estimated, and the presented method is appropriate for various types of modulators and interleavers.